Flip chip is an advanced semiconductor interconnection technology. It is also called as Controlled Collapse Chip Connection (C4) that a chip or die is flipped face down and bonded to the substrate with various interconnection materials. The technology is applicable to either single-chip packages or multiple-chip modules. In flip chip attachment, solder bumps deposited on a chip or die are used for electrical interconnection between a chip or an integrated circuit and a substrate. The substrate can be a silicon or ceramic or glass or printed circuit board (PCB) or some material composition substrate. When a chip or die with solder bumps is aligned to attach to a substrate, a reflow process of high temperature is performed to melt solder bumps. The solder bumps can form the solder joints to provide the electrical interconnection and the mechanical bonds between the chip and the substrate. There are many advantages that the flip chip provides, such as the shortest possible leads, lowest inductance, highest frequency, best noise control, highest density, greatest number of I/Os, smallest device footprints, and lowest profile.
The VLSI silicon technology and the integrated circuit design achieve a great progress. The integrated circuit chip sizes are continually shrinking, while circuit densities and I/O counts continue to increase. These trends require and drive the development of very high density I/O providing the interconnections in the integrated circuit modules. C4 solder bumps can form the solder joints that provide the high density interconnection between the chip and the substrate. This requires the very precise placement of each solder bump, uniform control of bump height as well as the very small space among solder bumps.
The solder bumps are fabricated directly on the metal pads that distribute on the surface of wafer. The pads are surrounded by the insulating and non-solderable layer with opening patterns. These pads connect with the integrated circuits in the wafer and are electrically isolated from each other. On the substrate (e.g. PCB or ceramic), flip chip attachment also requires the pads with the precise arrangement matching the solder bumps.
One method of forming solder bumps is introduced by IBM in the early 1960s. A metal mask with designed holes is placed over the wafer for depositing the solder bumps. The deposition process is performed in a vacuum chamber where the solder material is evaporated through the mask to deposit on the wafer. Due to the requirements of expensive equipments and complicated process control, the technique isn't used widely.
The electroplating-based flip chip process offers some advantages over other solder preparation methods. It is one of the most widely used methods. It is applicable to ultra-fine pitched I/Os, due to the accurate pattern transfer by the photolithographic process. This method is cheaper than the evaporation method because the expensive metal mask isn't needed and the plating process is simple. In comparison with other processes, the electroplating bumping process can achieve the solder material deposition on the fine-pitch I/O pads.
FIGS. 1a–1d show a known electroplating method of forming solder bumps on a wafer. Before the electroplating process, the metal pads 3 with designed patterns are deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD) (sputtering or evaporation) on the wafer 1. A passivation layer 2, an insolating material with opening patterns, is deposited to cover the metal pads 3. The electroplating bumping process requires a continuous electrically conductive seed layer 6 that is deposited on the wafer 1, as shown in FIG. 1a. The seed layer 6 provides the electroplating current for the deposition of solder material 15 during the electroplating process.
In order to improve the adhesion and reliability of solder bumps, a few metal films consist in a multi-layer under bump metallization (UBM) layer 16, which also act as part of the seed layer 6. The UBM layer 16 usually includes the first adhesion layer using either chromium (Cr), or titanium tungsten alloy (Ti—W). And the second metal layer 16 in the UBM layer 16 comprises either copper, or chromium copper alloy (Cr—Cu). A very thin good (Au) film is formed to protect the second layer from the oxidation. After the UBM layer 16 deposition process, the thick photoresist 14 with the designed patterns is coated on the wafer 1, as shown in FIG. 1b. The patterned photoresist 14 will provide the mask for the deposition of solder materials 15.
After the electroplating process, the desired volume of solder material 15 forms a mushroom-shape on the wafer 1, as shown in FIG. 1c. And then the photoresist 14 is removed and the solder material 15 remains. Tin-lead alloys (Sn/Pb) with various compositions are usually used as well as lead-free alloys, for example, tin-silver, tin-copper, tin-silver-copper, etc. The solder materials 15 can form solder bumps 4 through a melting or reflowing process. The melting or reflowing temperature depends on the alloy compositions. Before the reflowing process, the seed layer 6 among the solder materials 15 needs to be removed. The seed layer 6 may cause the electrical short and the solder collapse during the reflowing process. A chemical or electrolytic etching process is performed to remove the seed layer 6 among the solder materials 15. During the reflowing process, the solder material 15 melts and forms the solder bumps 4, as shown in FIG. 1d. 
The deposition of electroplated solder bump is determined by plating current density, temperature, electrolyte composition, additive and other process parameters. During the reflowing process, tin in the solder bumps 4 can react with the top metal of the UBM layer 16 to form an intermetallic compounds (IMC). The IMC layer can provide a mechanical bond between the solder bump 4 and the UBM layer 16. But the growth of thick IMC layer will degrade the reliability of solder bump 4 because the IMC layer is a brittle material and it can consume the UBM layer 16. The solder bumping process affects the growth of IMC and the thermal fatigue life of solder joints. Furthermore, the IMC layer thickens during device long-time storage and device operations even at room temperature. Under some loading conditions, cracks initiate and propagate easily at the interface of the solder and IMC layers resulting in mechanical failure of the joints.
The photoresist process is also an important factor. The reliability and the height uniformity of solder bumps are affected by the photolithography process. The thickness of photoresist 14 should reach an appropriate thickness to realize solder bumps 4 with required height. Low photoresist thickness during the electroplating process can cause bridging. The typical photolithography cannot achieve enough thick photoresist film to avoid the bridging between both of solders. And the pattern holes with straight vertical wall are provided by the costly and complex photoresist process.
After the electroplating process, the conventional UBM etching process removes some solder to affect the uniformity and quality of bumps. And the residue of etching process causes the bridging of solder bumps, specially, for the fine-pitch solder bumps. Therefore, it is necessary to invent a simple and low-cost solder bumping process.